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Core8051
Interrupt Detect
The interrupts int0a, int1a, and int2 to int7 are activated
by level and the active state is logic 1 (high). Each of
these interrupt pins must be held at a logic 1 value until
Core8051 starts to service the affected interrupt. The
user's software must take the appropriate action to clear
each interrupt request (by writing to external peripherals
via the external SFR interface).
External Interrupt Connection (int)
Table 41 displays the interrupt source connection.
Table 41 ? Interrupt Source Connection
Interrupt
ie0
ie1
Tf0
Tf1
Ri0
Ti0
int0a
int1a
int2
int3
int4
int5
int6
int7
Device
–
–
Timer 0
Timer 1
Serial 0
Serial 0
–
–
–
–
–
–
–
–
Source
External pin
External pin
–
–
–
–
External pin
External pin
External pin
External pin
External pin
External pin
External pin
External pin
Figure 20 on page 35 illustrates an overview of the
interrupt service routine hardware within Core8051,
including the polling sequence.
34
v6.0
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